Protection of low temperature isolation fill

ABSTRACT

A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.

BACKGROUND

The present invention generally relates to semiconductor fabricationmethods and devices. More specifically, the present invention relates totechniques to protect low temperature isolation materials that form highaspect ratio elements (e.g., isolation regions) of a semiconductordevice.

The advancement in semiconductor integrated circuit technology hasfacilitated continuous reduction of the physical footprint anddimensions of semiconductor devices formed on semiconductor wafers. As aresult, circuit density also continues to increase per chip. For a givenchip size, active circuit components, e.g., semiconductor devices, aretypically placed in close proximity to each other to maximize circuitdensity. Electrical isolation regions such as shallow trench isolation(STI) regions are typically formed in the wafer to electrically isolateneighboring semiconductor devices from one another.

SUMMARY

Embodiments of the present invention are directed to a method offabricating a semiconductor device. The method includes forming aplurality of semiconductor fins on an upper surface of a semiconductorsubstrate. The semiconductor fins are spaced apart from one another by arespective trench to define a fin pitch. The method further includesdepositing a gap filling isolation material in the trenches. The oxidematerial has a first etch resistance. The method further includesconverting a portion of the isolation material into a different secondisolation material that defines a protective layer having a second etchresistance that is greater than the first etch resistance. The methodfurther includes annealing the converted second material to furtherincrease the second etch resistance. The annealing operation includesexposing the converted second material to an annealing temperature thatis below 900 degrees Celsius (° C.).

One or more additional embodiments of the present invention are directedto a semiconductor structure that includes a plurality of semiconductorfins on an upper surface of a semiconductor substrate. The semiconductorfins spaced apart from one another by a respective trench to define afin pitch. A multi-layer electrical isolation region is contained ineach trench. The multi-layer electrical isolation region includes anoxide layer and a protective layer. The oxide layer includes a firstmaterial on an upper surface of the semiconductor substrate. Theprotective layer includes a second material on an upper surface of theoxide layer. The second material is different than the first material.

One or more additional embodiments of the present invention are directedto another method of fabricating a semiconductor device, the methodincluding forming a plurality of semiconductor fins on an upper surfaceof a semiconductor substrate. The semiconductor fins are spaced apartfrom one another by a respective trench to define a fin pitch. Themethod further includes depositing a gap filling oxide material in thetrenches. The oxide material has a first material etch rate. The methodfurther includes implanting silicon ions into the oxide material toconvert a portion of the oxide material into a different second materialthat defines a protective layer having a second material etch rate thatis lower than the first material etch rate.

One or more additional embodiments of the present invention are directedto another method of fabricating a semiconductor device. The methodcomprises forming a plurality of semiconductor fins on an upper surfaceof a semiconductor substrate. The semiconductor fins are spaced apartfrom one another by a respective trench to define a fin pitch. Themethod further includes depositing an oxide material in the trenches toform an oxide layer. The oxide material has a first etch resistance. Themethod further includes performing an ion implantation process toimplant ions into the oxide material to convert a portion of the oxidelayer into a second material to form a first protective layer having asecond etch resistance that is different from the first etch resistance.The method further includes applying a high density plasma (HDP) to asurface of the first protective layer to convert a portion of the firstprotective layer into a third material that is different from the oxidematerial and the second material. The third material serves as a secondprotective layer having a third etch resistance that is different fromthe first and second etch resistances. The method further includesannealing the structure at temperatures below 900° C. to furtherincrease the etch resistance of both second material and the thirdmaterial. A combination of the annealed second material and the annealedthird material defines a multi-layer electrical isolation region.

One or more additional embodiments of the present invention are directedto another semiconductor structure that includes a plurality ofsemiconductor fins on an upper surface of a semiconductor substrate. Thesemiconductor structure comprises a plurality of semiconductor fins onan upper surface of a semiconductor substrate. The semiconductor finsare spaced apart from one another by a respective trench to define a finpitch. An oxide material is located in the trenches to define an oxidelayer. The oxide material has a first etch resistance. A second materialdifferent from the oxide material is located on an upper surface of theoxide layer to define a first protective layer. A third material islocated on an upper surface of the first protective layer. The thirdmaterial is different from the oxide material and the second material todefine a second protective layer. A combination of the oxide layer, thefirst protective layer and the second protective layer defines amulti-layer electrical isolation region that electrically isolates theplurality semiconductor fins from one another. Each of the oxide layer,the first protective layer and the second protective layer havingdifferent etch resistances with respect to one another.

Additional technical features and benefits are realized through thetechniques of the present invention. Embodiments and aspects of theinvention are described in detail herein and are considered a part ofthe claimed subject matter. For a better understanding, refer to thedetailed description and to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The specifics of the exclusive rights described herein are particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other features and advantages ofthe embodiments of the invention are apparent from the followingdetailed description taken in conjunction with the accompanying drawingsin which:

FIG. 1 illustrates a semiconductor structure according to a non-limitingembodiment of the invention;

FIG. 2 illustrates the semiconductor structure following deposition of afin protection liner according to embodiments of the invention;

FIG. 3 illustrates the semiconductor structure after depositing a lowtemperature isolation material according to embodiments of theinvention;

FIG. 4 illustrates the semiconductor structure undergoing a curingprocess according to embodiments of the invention;

FIG. 5 illustrates the semiconductor structure following achemical-mechanical planarization (CMP) process according to embodimentsof the invention;

FIG. 6 illustrates the semiconductor structure after recessing the lowtemperature isolation material according to embodiments of theinvention;

FIG. 7 illustrates the semiconductor structure undergoing a surfacetreatment operation according to embodiments of the invention;

FIG. 8 illustrates the semiconductor structure following the surfacetreatment operation according to embodiments of the invention;

FIG. 9 illustrates the semiconductor structure undergoing an optionalsubsequent nitrogen plasma treatment;

FIG. 10 illustrates the semiconductor structure undergoing thedensification anneal of low temperature isolation material;

FIG. 11 illustrates the semiconductor structure undergoing an ionimplantation operation according to embodiments of the invention;

FIG. 12 illustrates the semiconductor structure following the ionimplantation operation according to embodiments of the invention;

FIG. 13 illustrates the semiconductor structure undergoing a first ionimplantation operation according to embodiments of the invention;

FIG. 14 illustrates the semiconductor structure following the first ionimplantation process according to embodiments of the invention;

FIG. 15 illustrates the semiconductor structure undergoing a second ionimplantation process according to embodiments of the invention;

FIG. 16 illustrates the semiconductor structure following the second ionimplantation process according to embodiments of the invention; and

FIG. 17 illustrates the semiconductor structure of FIG. 16 undergoingthe densification anneal of low temperature isolation material followingthe second ion implantation process; and

FIG. 18 illustrates the semiconductor structure after removing the finprotection liner from exposed upper portions of the semiconductor finsaccording to embodiments of the invention.

The diagrams depicted herein are illustrative. There can be manyvariations to the diagram or the operations described therein withoutdeparting from the spirit of the invention. For instance, the actionscan be performed in a differing order or actions can be added, deletedor modified. Also, the term “coupled” and variations thereof describeshaving a communications path between two elements and does not imply adirect connection between the elements with no interveningelements/connections between them. All of these variations areconsidered a part of the specification.

In the accompanying figures and following detailed description of thedescribed embodiments, the various elements illustrated in the figuresare provided with two or three digit reference numbers. With minorexceptions, the leftmost digit(s) of each reference number correspond tothe figure in which its element is first illustrated.

DETAILED DESCRIPTION

Various embodiments of the invention are described herein with referenceto the related drawings. Alternative embodiments of the invention can bedevised without departing from the scope of this invention. Variousconnections and positional relationships (e.g., over, below, adjacent,etc.) are set forth between elements in the following description and inthe drawings. These connections and/or positional relationships, unlessspecified otherwise, can be direct or indirect, and the presentinvention is not intended to be limiting in this respect. Accordingly, acoupling of entities can refer to either a direct or an indirectcoupling, and a positional relationship between entities can be a director indirect positional relationship. Moreover, the various tasks andprocess steps described herein can be incorporated into a morecomprehensive procedure or process having additional steps orfunctionality not described in detail herein.

The following definitions and abbreviations are to be used for theinterpretation of the claims and the specification. As used herein, theterms “comprises,” “comprising,” “includes,” “including,” “has,”“having,” “contains” or “containing,” or any other variation thereof,are intended to cover a non-exclusive inclusion. For example, acomposition, a mixture, process, method, article, or apparatus thatcomprises a list of elements is not necessarily limited to only thoseelements but can include other elements not expressly listed or inherentto such composition, mixture, process, method, article, or apparatus.

Additionally, the term “exemplary” is used herein to mean “serving as anexample, instance or illustration.” Any embodiment or design describedherein as “exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments or designs. The terms “at least one”and “one or more” can include any integer number greater than or equalto one, i.e. one, two, three, four, etc. The terms “a plurality” can beunderstood to include any integer number greater than or equal to two,i.e. two, three, four, five, etc. The term “connection” can include bothan indirect “connection” and a direct “connection.”

The terms “about,” “substantially,” “approximately,” and variationsthereof, are intended to include the degree of error associated withmeasurement of the particular quantity based upon the equipmentavailable at the time of filing the application. For example, “about”can include a range of ±8% or 5%, or 2% of a given value.

For the sake of brevity, conventional techniques related to making andusing aspects of the invention may or may not be described in detailherein. Accordingly, in the interest of brevity, many conventionalimplementation details and fabrication techniques are only mentionedbriefly herein or are omitted entirely without providing the well-knownsystem and/or process details.

Turning now to an overview of technologies that are more specificallyrelevant to aspects of the invention, the process of forming electricalinsulation or isolation regions, such as shallow trench isolation (STI)regions, involves forming insulator-filled trenches between activesemiconductor components and/or conductive lines. The trenches have anaspect ratio that is typically defined as the measured trench heightwith respect to the measured trench width. However, as circuit densitiescontinue to increase, the dimensions of these trenches decrease therebyincreasing the aspect ratio of the trenches. As a result, filling thesenarrower trenches (referred to as high-aspect ratio trenches) becomesmore difficult and can lead to unwanted voids and discontinuities in theinsulating or trench-fill material.

The presence of high aspect ratio semiconductor components and deviceelements such as high aspect ratio STI regions, for example, hasresulted in the utilization of various high aspect ratio trench fillingtechniques. One such technique for forming a high aspect ratio STIregion includes filling a high aspect ratio trench with alow-temperature oxide material which reduces the formation of voids anddiscontinuities. Although STI region formation is described herein, itshould be appreciated that the above-mentioned techniques can beapplicable to other isolation layers beyond STI, for example forisolation between transistor gates in middle of line.

The low-temperature oxide material is typically, silicon oxide, but isnot limited to silicon oxide. Typically, a gap filling technique is usedfor isolation film deposition, which is capable of filling narrowtrenches. For example, the spin-on material or the CVD process whichallows the isolation material to become fluid and flowable is used tofill the narrow gap in conjunction with non-conformal high densityplasma deposition (HDP). Such deposition methods are capable of fillingnarrow trenches “bottom-up”. Excepting HDP CVD, these low-temperatureoxide materials, however, typically have low-etch resistance andtherefore can be unintentionally over-etched or pulled-down whenperforming subsequent cleaning techniques or other downstreamfabrication processes. The unintentional pull-down of the resulting STIregion can cause device defects and undesirable device variability.

In addition, traditional low temperature isolation materials typicallyhave relatively poor density and high wet etch rate (several times ofthat of high quality thermal oxide), and therefore are referred to aslow quality oxide material. The properties of these traditional lowtemperature isolation materials can be improved by annealing the lowtemperature isolation material in steam or neutral (nitrogen) ambient attemperature above 1000 degrees Celsius (° C.). However, the modifiedproperties rapidly deteriorate with a reduced thermal budget, i.e.,annealing temperature below 1000° C., and modern technologies oftenrequire lower total temperature budget (i.e., annealing temperature thatare less than e.g., 800° C.). Consequently, it has proven difficult toproduce high-quality isolation oxide materials (e.g., oxide materialshaving relatively high density and low wet etch rates) using lowannealing temperatures.

Turning now to an overview of the aspects of the invention, one or moreembodiments of the invention address the above-described shortcomings ofthe prior art by forming a protective layer at the top portion of thelow temperature gap fill material that forms a high aspect ratio deviceelement to prevent unintentional damage such as, for example,over-etching or pull-down. In one or more embodiments of the invention,the protective layer is formed by modifying or converting a portion ofthe low temperature gap fill material into a high-resistive materialcapable of withstanding various etchant chemistries employed duringpre-cleaning or other downstream fabrication processes. In addition, oneor more non-limiting embodiment provides a method of improving isolationmaterial properties of oxide isolation fill materials using an annealprocess that applies temperature that do not exceed an 800° C. totaltemperature limit. Accordingly, high aspect semiconductor deviceelements such as high aspect ratio STI regions, for example, can beformed free of unwanted voids and discontinuities, while the structuralintegrity of these high aspect device elements are maintained afterperforming subsequent downstream fabrication processes.

Turning now to a more detailed description of aspects of the presentinvention, FIG. 1 depicts a semiconductor structure 100 according to anon-limiting embodiment. The semiconductor structure includes asubstrate 102, and a plurality of semiconductor fins 104 formed on thesubstrate 102 following one or more semiconductor fin fabricationprocesses. Hardmask caps 101 can also be formed on the upper surface ofthe semiconductor fins 104. The hardmask caps 101 can be composed of anitride material such as silicon nitride (SiN), for example, and canserve to protect the fins 104 during subsequent fabrications processes.

The fin fabrication processes includes, for example, a photolithographicpatterning process, followed by an etching process such as reactive ionetching (ME) process. The etching process transfers thephotolithographic pattern into the substrate 102 and forms thesemiconductor fins 104 as illustrated in FIG. 1. Although threesemiconductor fins 104 are illustrated in FIG. 1, the substrate 102 cancontain additional fins 104 that define a high-density arrangement ofsemiconductor fins 104. For example, the semiconductor fins 104 can beseparated from one another by trenches 105. The distance (D) betweeneach fin 104 can range, for example, from approximately 10 nm toapproximately 50 nm to define a high-density fin pitch, or high-densityarrangement of semiconductor fins 104 on the substrate 102. Thehigh-density fin pitch defined by distance D makes it very difficult tofill the trenches 105 using a non-flowable oxide fill process.

Non-limiting examples of desirable materials for the substrate 102include Si (silicon), strained Si, SiC (silicon carbide), Ge(germanium), SiGe (silicon germanium), SiGeC (silicon-germanium-carbon),Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide),InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide(AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmiumsulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zincselenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or anycombination thereof. Other non-limiting examples of semiconductormaterials include III-V materials, for example, indium phosphide (InP),gallium arsenide (GaAs), aluminum arsenide (AlAs), or any combinationthereof. The III-V materials can include at least one “III element,”such as aluminum (Al), boron (B), gallium (Ga), indium (In), and atleast one “V element,” such as nitrogen (N), phosphorous (P), arsenic(As), antimony (Sb). In addition, it should be appreciated that althougha bulk substrate 102 is illustrated in FIG. 1, the substrate 102 canalso be formed as a semiconductor-on-insulator (SOI) substrate withoutdeparting from the scope of the invention.

Turing to FIG. 2, the semiconductor structure 100 is illustratedfollowing deposition of a fin protection liner 106. The fin protectionliner 106 is deposited on an upper surface of the substrate 102, andconforms to the sidewalls and upper surface of the semiconductor fins104. The fin protection liner 106 can be formed using a chemical vapordeposition (CVD) process or thermally grown with or without theassistance of plasma excitation, for example, and is composed of a linermaterial including, but not limited to Si, silicon oxide or siliconnitride (SiN).

Referring to FIG. 3, the semiconductor structure 100 is illustratedafter depositing a low temperature isolation material 108 on an uppersurface of the fin protection liner 106 to fill the trenches 105 andcover the semiconductor fins 104. In one or more non-limitingembodiment, the low temperature isolation material 108 has a thermalbudget for deposition of less than about 500 degrees Celsius (° C.). Thelow temperature isolation material 108 can be formed of various oxide oroxide-like materials having a dielectric constant (k) of approximately3.9, for example, or lower. In one or more embodiments, the lowtemperature isolation material 108 is composed of silicon dioxide (SiO₂)or nominally SiO₂, for example, and is deposited using a flowabledielectric deposition process. It should be appreciated, however, thatother deposition processes capable of depositing the low temperatureisolation material 108 be used without departing from the scope of theinvention.

In one or more non-limiting embodiments, the trenches 105 can be filledwith other low temperature isolation materials (e.g., other than SiO₂)having the following electrical properties: Leakage at about 1 MV lessthan about 1 e⁻⁸ A/cm² and less than about 1 e⁻⁷ A/cm² at 2 MV;Dielectric Breakdown is greater than about 6 MV/cm; and the dielectricconstant (k value) is below about 5. The material composition caninclude, but is not limited to, silicon (Si), carbon (C), boron (B),nitrogen (N) and Oxygen (O).

In one or more embodiments, a post-deposition heat treatment, alsoreferred to as a post-anneal process, can be performed to increase theetch resistance (i.e., reduce the etch rate) of the modified lowtemperature isolation material. The post-anneal process exposes themodified low temperature isolation material to temperature above 1000°C., for example. In at least one non-limiting embodiment, a two-steppost-deposition anneal process is performed. The two-step post-annealprocess includes a first operation that applies heat using steam (watervapor) to anneal the modified low temperature isolation material toabout 600° C., followed by a second, higher temperature anneal processup to 800° C.

Turning to FIG. 4, the semiconductor structure 100 is illustratedundergoing a curing process to cure the low temperature isolationmaterial 108. The curing process includes, but is not limited to, a UVenergy exposure process, a thermal anneal process, and a laser annealprocess. A subsequent steam and/or dry nitrogen (N₂) anneal process canalso be applied to the low temperature isolation material 108.

Turning now to FIG. 5, the semiconductor structure 100 is illustratedfollowing a chemical-mechanical planarization (CMP) process. The CMPprocess can be performed to recess a portion of the low temperatureisolation material 108 while stopping on the hardmask or the finprotection liner 106 formed on the upper surface of the fins 104. TheCMP process can serve to remove overburden or excess low temperatureisolation material 108 from the semiconductor fins 104.

With reference now to FIG. 6, the semiconductor structure 100 isillustrated following an etching process that recesses an upper portionof the low temperature isolation material 108 to reveal a portion ofsemiconductor fins 104. In one or more embodiments, the isolationmaterial 108 can be recessed using a RIE process or a wet etchingprocess. The ME can employ a chemistry that is selective to theisolation material 108. In this manner, the low temperature isolationmaterial 108 is recessed while the hardmask and the fin protection liner106 are preserved as illustrated in FIG. 6. The preserved fin protectionliner 106 can serve to protect the underlying semiconductor fins 104from becoming damaged when performing one or more subsequent fabricationprocesses described in greater detail below. As an alternative to RIE, awet etching process including a Hydrofluoric (HF) acid chemistry, suchas diluted HF (DHF), for example, can be used.

The remaining portions of the low temperature isolation material 108separating one or more semiconductor fins 104 can be referred to aselectrical isolation regions 110 such as, for example, STI regions, andcan serve to electrically isolate neighboring transistor structures thatare formed during a subsequent fabrication process (not shown). In oneor more embodiments, the electrical isolation regions 110 can beimplemented when design applications call for neighboring gates thathave opposite conductivities, e.g., nFETs and pFETs. As such, theelectrical isolation regions 110 can electrically isolate an nFET deviceregion from a pFET device region.

Referring to FIG. 7, a surface treatment operation (indicated by thedownward arrows) is applied to an upper surface of the low temperatureisolation material 108. The surface treatment operation modifies orconverts a portion of the low temperature isolation material 108 into ahigh-quality material. The high-quality material refers to the convertedmaterial's increased resistance, which allows the converted high-qualitymaterial to withstand various etchant chemistries employed duringpre-cleaning or other downstream fabrication processes. Etch resistancecan also be determined in terms of a material's etch rate. For instance,a material's etch rate decreases as its etch resistance increases. Theetch rate of stoichiometric thermal SiO₂ undergoing a diluted (10:1 byvolume) hydrofluoric (DHF) acid etching treatment, for example, isnominally 20 angstroms per min (20 A/min) or 2 nanometers per minute (2nm/min). Accordingly, one or more embodiments of the invention initiallydeposit a low temperature isolation material 108 having an etch rategreater than about two-times (×2) that of stoichiometric thermal SiO₂.

In one or more embodiments, the surface treatment operation includesapplying nitrogen-containing plasma (e.g., a nitrogen plasma orammonia-based plasma) when the low temperature isolation material 108 iscomposed of SiO₂. Other plasma species, however, can be employedincluding, but not limited to, helium (He), hydrogen (H), argon (Ar),and oxygen (O). The fin protection liner 106 serves to protect theunderlying low temperature isolation material 108.

In one or more embodiments of the invention, a high density plasma (HDP)treatment is performed to densify (i.e., increase the density) of adeposited low temperature isolation fill material. The HDP can beapplied using an inductively coupled plasma (ICP) generated by an HDPreactor.

In one or more embodiments of the invention, a combination of HDPtreatments can be performed. Following the HDP treatments, a posttreatment anneal below 800° C. nitrogen ambient, for example, can thenbe performed to improve wet etch rate of the deposited insulatingmaterial significantly. In one example, the wet etch rate of thedeposited insulating material was decreased from about 2 times the etchrate of thermal oxide (e.g., about 40 A per minute) to about 25 A perminute, which is closer the quality of that of thermal oxide (e.g., 20 Aper minute).

In one or more embodiments of the invention, a combination of helium andoxygen (He+O₂) plasma treatment or a combination of hydrogen and oxygen(H₂+O₂) plasma treatment can be applied to the low temperature isolationmaterial 108. The helium and hydrogen plasma flow can be delivered atabove 1000 standard cubic centimeters per minute (sccms). The treatmentcan be applied for less than 5 minutes, for example, with a plasma powerless than about 5000 watts (W). In at least one embodiment, a smallamount (less than 50 sccms) of argon (Ar) can be added to the plasma toensure stability.

In one or more embodiments of the invention, a plasma treatmentincluding nitrogen can be applied to the low temperature isolationmaterial 108 to change the composition of oxide and add nitrogen. Theheat up step applying argon (Ar) and/or helium (He) can be applied forabout 2 minutes, for example, with plasma power of about 3000 Watts, forexample. After the pre-heat step, a main nitrogen plasma treatment stepcan be performed for a second plasma time (e.g., less than 10 min) withHe as additional gas. A plasma power less than about 10 kilowatts (kW)can be used, for example, with zero or very small bias (e.g., about fewhundred Watts). The process temperature can be selected depending onplasma power and can be below 50° C. for any of the HDP treatmenttreatments described herein.

With reference now to FIG. 8, the electrical isolation regions 110 areillustrated having a protective layer 112 which results from modifyingor converting a portion of the low temperature isolation material 108.The protective layer 112 is formed above the remaining non-modified lowtemperature isolation material 108. Accordingly, the electricalisolation regions 110 can be viewed as being modified into multi-layerelectrical isolation regions 110. In other words, each multi-layerelectrical isolation region 110 can be viewed as including a lowtemperature isolation layer 108 and a protective layer 112 formed on anupper surface of the low temperature isolation layer 108.

In the non-limiting embodiment of FIG. 8, the surface treatmentoperation (i.e., the plasmas treatments) modifies or converts an upperportion of the low temperature isolation dielectric material (e.g.,SiO₂) into the protective layer 112 composed of an oxy-nitride (SiOxNy)material. The protective layer 112 resulting from the plasma treatmentcan have a thickness (Th1) ranging, for example, from approximately 0.5nm to approximately 10 nm. The oxy-nitride protective layer 112 has ahigher etching resistance compared to the remaining non-modified bottomlayer 108. In at least one embodiment, the non-modified oxide layer 108has an etch rate that is more than two-times (×2) greater thanstoichiometric thermal SiO₂ when undergoing a 10:1 diluted HF (DHF) acidetching treatment, for example, while the second material of theprotective layer has an etch rate that is about 1.5 times greater thanstoichiometric thermal SiO₂ when undergoing a DHF etching treatment.Accordingly, the protective layer 112 has an etch resistance that isgreater than the etch resistance of the remaining non-modified oxidelayer 108.

In the case where the low temperature isolation material is composed ofSiO₂, for example, the modified oxy-nitride protective layer 112 has awet etch resistance that is at least twice (x2) over the etch resistanceprovided by SiO₂. Accordingly, a portion of the low temperatureisolation material 108 can be modified or converted into a protectivelayer 112, which can then serve as a mask to protect the remainingunderlying low temperature isolation material 108. Thus, no additionalmaterial deposition processes are required to form a separate highquality protective layer on top of the low temperature isolationmaterial 108. As described herein, the term “high quality” refers to thelow temperature isolation layer's 108 increased resistance to variousetchant chemistries which can be employed during pre-cleaning or otherdownstream fabrication processes.

The elimination of a separate deposition process also improves theprecision at which the electrical isolation regions 110 are formed. Forexample, the height of the electrical isolation regions 110 is notsubsequently increased because the underlying low temperature isolationmaterial 108 can be protected without depositing additional materials.Also, the multi-layer electrical isolation region 110 can also be formedfree of physical interfaces or contact surfaces between the lowtemperature isolation material 108 and the protective layer 112 becausethe protective layer 112 is converted directly from the low temperatureisolation material 108 and therefore can be integrated therewith.

In one or more embodiments of the invention, the plasma treatmentincluding nitrogen can be utilized as an optional subsequent plasmatreatment that is performed after an initial plasma treatment (e.g., thehelium and oxygen (He+O₂) combination plasma treatment or afterperforming an initial hydrogen and oxygen (H+O₂) combination plasmatreatment). Accordingly, nitrogen elements are introduced into theinitially modified portion of the protective layer 112 (see FIG. 9).

Turning to FIG. 10, the semiconductor device 100 is illustratedundergoing a thermal anneal process after forming the protective layer112. The thermal anneal process anneals the converted oxide material ofthe protective layer 112 at temperatures below approximately 900° C. soas to increase the density of the protective layer 112. In at least oneembodiment, the protective layer 112 reaches a temperature ranging fromabout 500° C. to about 800° C. In this manner, etch resistance of theprotective material 112 is increased thereby further reducing thematerial's etch rate. Alternatively the anneal process can be performedat an earlier step. For example, the anneal process can be performedprior to revealing the fins 104 (see FIG. 5).

Turning now to FIG. 11, the semiconductor device 100 is illustratedundergoing an ion implantation operation (indicated by the downwardarrows) to form multi-layer electrical isolation regions 110 accordingto another non-limiting embodiment. In this embodiment, ions 114(indicated by the downward arrows) are implanted into the lowtemperature isolation material 108, while the hardmask and finprotection liner 106 serve to protect the underlying fins 104.

Unlike plasma treatments, the ions delivered during the ion implantprocess can penetrate deep into the low temperature isolation material108, thereby forming a deep protective layer with improved properties.The deep penetration of the ions also allows for modifying the fullthickness of the low temperature isolation material 108. The ions 114can include various types or chemical species including, but not limitedto, nitrogen (N), helium (He), hydrogen (H), and argon (Ar) or silicon(Si). Unlike a traditional plasma treatment, the energy of the ionimplantation process can be varied to control the depth at which theions 114 are implanted into the low temperature isolation material 108.

When the fins 104 are formed from Si, for example, an ion implantationprocess that implants silicon (Si) ions can be performed to avoidcontaminating the Si fins 104 with a counteracting material. In thisexample, the Si ions form a silicon-rich insulating material, which hasa wet etch rate that is lower than traditional thermal oxide materials.In one or more embodiments of the invention, silicon implant energiescan range, for example, from about 2 kilo-electronvolts (keV) to about35 keV, and doses can range, for example, from e¹³ to e¹⁵ at/cm2.

Referring to FIG. 12, multi-layer electrical isolation regions 110 areillustrated following the aforementioned ion implantation process. Themulti-layer electrical isolation regions 110 each include a protectivelayer 116 formed above a non-modified portion of the low temperatureisolation material 108. In the non-limiting embodiment of FIG. 10, theimplanted nitrogen ions modify or convert a portion of the lowtemperature isolation material (e.g., SiO₂) into the protective layer116 composed of an oxy-nitride (SiOxNy) material. The oxy-nitrideprotective layer 116 has a higher etching resistance compared to theremaining non-modified low temperature isolation material 108. Inaddition, the modified oxy-nitride protective layer 116 has a greaterdensity than the remaining underlying low temperature isolation material108.

As described above, the modified oxy-nitride protective layer 116 has awet etch resistance that is least twice (x2) over the etch resistanceprovided by the SiO₂ non-modified low temperature isolation material108. Accordingly, a portion of the low temperature isolation material108 can be modified into a protective layer 116, which can then serve asa mask to protect the remaining underlying low temperature isolationmaterial 108. Thus, no additional material deposition processes arerequired to form a separate layer on top of the low temperatureisolation material 108. The elimination of a separate deposition processalso improves the precision at which the electrical isolation regions110 are formed. For example, the height of the electrical isolationregions 110 is not subsequently increased because the underlying lowtemperature isolation material 108 can be protected without depositingadditional materials. Also, the multi-layer electrical isolation region110 can also be formed free of physical interfaces between the lowtemperature isolation material 108 and the protective layer 116 becausethe protective layer 116 is converted directly from the low temperatureisolation material 108 and therefore is integrated therewith.

As described above, the energy level used to implant the ions 114 can bevaried to control a thickness (Th2) of the protective layer 116.Accordingly, the protective layer 116 can be formed at greater depths inthe electrical isolation regions 110 compared to the protection layer112 formed using the plasma treatment operation described above. Forexample, the protective layer 116 resulting from the ion implantationprocess can have a thickness (Th2) ranging from approximately 0.5 nm toapproximately 100 nm. In other non-limiting embodiments, the entire lowtemperature isolation material 108 can be modified such that theprotective layer 116 reaches the base of the electrical isolationregions 110 located near the substrate 102. In another example, thethickness (Th2) of the protective layer 116 can be greater than athickness of the non-modified temperature isolation material 108.

In addition, the ion implantation technique can be used to implantdifferent types of ions or different chemical species at differentdepths within the electrical isolation regions 110. In this manner, amulti-layer electrical isolation region 110 can be formed having severaldifferent protective layers, with each protective layer composed of adifferent material or different chemical species.

Referring to FIG. 13, for example, a first ion implantation process isperformed. The first ion implantation process includes implanting afirst ion type 114 a or chemical species 114 a into the low temperatureisolation material 108 (e.g., SiO₂) located in the electrical isolationregions 110. The first type of ions 114 a can include, but are notlimited to silicon (Si). In addition, the first ion implantation processimplants the first ions 114 a according to a first energy level so thatthe depth (e.g., distance extending from the upper surface into the lowtemperature isolation material 108) of the resulting first protectivelayer (not shown in FIG. 11) can be controlled.

Turning to FIG. 14, the semiconductor device 100 is illustrated having afirst protective layer 116 a formed according to the first ionimplantation process. Referring to the example described in FIG. 11,implantation of Si ions 114 a into the low temperature isolationmaterial 108 composed of SiO₂ forms a silicon-rich (Si_(x)O_(y))protective layer 116 a. The Si-rich protect layer 116 a can be viewed ashaving higher levels of Si than the non-modified SiO₂ low temperatureisolation material 108. In addition, the Si-rich protective layer 116 acan have increased thermal and/or etch resistance compared to thenon-modified SiO₂ low temperature isolation material 108. The firstprotective layer 116 a also reaches a first depth determined by theenergy level used to implant the first ions 114 a to define a firstthickness (D₁I).

Referring now to FIG. 15, a second ion implantation process isperformed. The second ion implantation process includes implanting asecond type of ions 114 b or chemical species into the first protectivelayer 116 a located in the electrical isolation regions 110. The secondtype of ions 114 b can include, but are not limited to, nitrogen (N),helium (He), hydrogen (H), and argon (Ar). The energy level of thesecond ion implantation process can be adjusted (e.g., reduced) suchthat the second ions 114 b can be implanted at a selected depth inrelation to the first protective layer 116 a.

Turning now to FIG. 16, the semiconductor device 100 is illustratedhaving a second protective layer 116 b formed according to the secondion implantation process. The second protective layer 116 b is composedof a different material with respect to the first protective layer 116a. For example, implantation of N ions into the Si-rich (Si_(x)O_(y))protective layer 116 a forms an oxy-nitride (Si_(x)O_(y)N_(z))protective layer 116 b. The second protective layer 116 b also reaches asecond depth determined by the energy level used to implant the secondions 114 b. In the example illustrated in FIGS. 13 and 14, the seconddepth of the second protective layer 116 b is less than the first depthof the first protective layer 116 a. Accordingly, the second protectivelayer 116 b is formed having a second thickness (Di2). Because a portionof the first protective layer 116 a is converted into the secondprotective layer 116 b, the original thickness (Dil) of the firstprotective layer 116 a can be viewed as being reduced (Dil′) followingthe second ion implantation process.

In another embodiment, a plasma treatment operation can be applied tothe upper surface of the Si-rich (Si_(x)O_(y)) protective layer 116 a.In this manner, an upper portion of the Si-rich (Si_(x)O_(y)) protectivelayer 116 a is converted into a second protective layer 116 b. Forexample, an upper portion of the Si-rich (Si_(x)O_(y)) protective layer116 a can be converted to an oxy-nitride (Si_(x)O_(y)N_(z)) protectivelayer 116 b when plasma containing a nitrogen species is appliedthereto.

In either scenario described above, the oxy-nitride (Si_(x)O_(y)N_(z))protective layer 116 b resulting from the nitridation of oxide providesgreater etching resistance compared to the Si-rich oxide (Si_(x)O_(y))protective layer 116 a and the original low temperature dielectricmaterial (e.g., SiO₂). Accordingly, a multi-layer electrical isolationregion 110 can be formed having several different protective layers 116a and 116 b. Each protective layer 116 a and 116 b can be composed of adifferent material, e.g., Si_(x)O_(y) and Si_(x)O_(y)N_(z),respectively, and therefore can provide different wet etch resistancecharacteristics at selected layers or levels of the multi-layerelectrical isolation region 110. Although the first and secondprotective layers 116 a and 116 b are illustrated as distinct individuallayers, it should be appreciated that the ions 114 a and 114 bcorresponding to the respective protective layer can be deposited toform a gradient composition of chemical species extending from the lowtemperature isolation material layer 108 to the upper surface of thesecond protective layer 116 b.

Turning to FIG. 17, the semiconductor device 100 is illustratedundergoing a densification anneal of the first and second protectivelayers 116 a and 116 b. The densification anneal includes applyingheated steam to the low temperature isolation material 108. in at leastone embodiment, the low temperature isolation material 108 is heated toa temperature ranging from about 500° C. to about 800° C. Accordingly,the density of the first and second protective layers 116 a and/or 116 blayers is increased such that the etch rate of the first and secondprotective layers 116 a and 116 b is decreased.

Although embodiments described above initially perform a deepimplantation process to form the first protective layer 116 a prior toforming the second modified layer 116 b, the invention is not limitedthereto. For instance, a surface treatment (e.g., plasma treatment) canbe performed first to convert a first portion of the low temperatureisolation material layer 108 into oxy-nitride (SiO_(x)N_(y)) protectivesurface layer. Thereafter, a subsequent ion implantation process can beperformed to form an underlying second portion of the low temperatureisolation material layer 108 (i.e., located beneath the convertedSiO_(x)N_(y) protective surface layer) into a Si-rich oxide(Si_(x)O_(y)) protective layer.

Turning to FIG. 18, the semiconductor device 100 is illustratedfollowing removal of the fin protection liner 106 from exposed portionsof the semiconductor fins 104 located above the upper surface of themulti-layer electrical isolation region 110. The etching process can usevarious etching chemistries selective to the material of the finprotection liner 106. For example, a heated phosphoric acid etchant canbe applied to the semiconductor fins 104 to remove a fin protectionliner 106 composed of silicon nitride (SiN) while preserving theunderlying semiconductor fins 104 and second protective layer 116 b. ARIE process that utilizes chemistries selective to the selected materialof the fin protection liner 106 can also be employed. Although thehardmask caps 101 are shown as being maintained following partialremoval of the fin protection liner 106, it should be appreciated thatthe hardmask caps 101 can also be removed from the upper surfaces of thefins 104 at this stage.

Although removal of the fin protection liner 106 is described afterperforming the two different ion implantation processes described above,the stage at which the fin protection liner 106 can be removed is notlimited thereto. For example, the fin protection liner 106 can beremoved after performing the plasma technique used to form protectivelayer 112 (see e.g., FIG. 9). In another example, the fin protectionliner 106 can be removed after performing the single ion implantationprocess used to form the single protective layer 116 (see e.g., FIG.12).

As described herein, one or more embodiments of the invention modify orconvert a portion of a low temperature isolation fill material used toform a high aspect ratio device element (e.g., a high aspect ratio STIregion) into a high-resistive protective layer capable of withstandingvarious etchant chemistries employed during pre-cleaning or otherdownstream fabrication processes. Accordingly, a resulting high aspectratio semiconductor device element can be formed from a low temperatureisolation material while being protected from downstream cleaningprocesses and other subsequent fabrication operations. In some examples,high aspect trenches can be filled using a low temperature isolationmaterial to form high aspect STI regions. Accordingly, these resultingSTI regions can be formed without voids or other deficiencies commonlypresent when using non-flowable oxide fill processes, but are protectedfrom unintentional over-etching and pull-down due to the modifiedprotective layer.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments describe. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdescribed herein.

1. (canceled)
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 7. A semiconductor structure comprising: a plurality ofsemiconductor fins on an upper surface of a semiconductor substrate, thesemiconductor fins spaced apart from one another by a respective trenchto define a fin pitch; and a multi-layer electrical isolation regioncontained in each trench, the multi-layer electrical isolation regioncomprising: an oxide layer comprising of a first material on an uppersurface of the semiconductor substrate; a protective layer comprising asecond material on an upper surface of the oxide layer, the secondmaterial being different than the first material; a fin protection linerformed on the plurality of semiconductor fins, the fin protection linercomprising a third material that is different from the second materialof the protective layer comprising, the fin protection liner including alower portion interposed between the semiconductor substrate and theoxide layer and an upper portion on sidewalls and an upper surface ofthe plurality of semiconductor fins, wherein the protected layer isdirectly on the oxide layer.
 8. The semiconductor structure of claim 7,wherein the second material is an annealed oxide material.
 9. Thesemiconductor structure of claim 8, wherein the first material has afirst etch resistance and the second material has a second etchresistance that is greater than the first etch resistance.
 10. Thesemiconductor structure of claim 9, wherein the first material comprisesnominally stoichiometric silicon dioxide (SiO₂), and wherein the secondmaterial is an oxide material containing nitrogen.
 11. The semiconductorstructure of claim 10, wherein the second material is modified siliconoxide containing species selected from a group comprising nitrogen (N),helium (He), hydrogen (H), and argon (Ar), and Oxygen.
 12. Thesemiconductor structure of claim 9, wherein the first material comprisesnominally stoichiometric silicon dioxide (SiO₂), and the second materialwhich is modified SiO2.
 13. (canceled)
 14. (canceled)
 15. (canceled) 16.(canceled)
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 18. (canceled)
 19. (canceled)
 20. (canceled)21. (canceled)
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 23. (canceled)
 24. A semiconductorstructure comprising: a plurality of semiconductor fins on an uppersurface of a semiconductor substrate, the semiconductor fins spacedapart from one another by a respective trench to define a fin pitch; anoxide material in the trenches to define an oxide layer, the oxidematerial having a first etch resistance; a second material differentfrom the oxide material on an upper surface of the oxide layer to definea first protective layer, the first protective layer containing plasmaspecies implanted therein in response to undergoing a plasma treatment;a third material on an upper surface of the first protective layer, thethird material different from the oxide material and the second materialto define a second protective layer; a fin protection liner formed onthe plurality of semiconductor fins, the fin protection liner comprisinga fourth material that is different from the oxide material of the oxidelayer, the second material of the first protective layer, and the thirdmaterial of the second protective layer, wherein a combination of theoxide layer, the first protective layer and the second protective layerdefines a multi-layer electrical isolation region that electricallyisolates the plurality semiconductor fins from one another, and whereineach of the oxide layer, the first protective layer and the secondprotective layer having different etch resistances with respect to oneanother.
 25. The semiconductor structure of claim 24, wherein the firstprotective layer has an etch resistance that is greater than the oxidelayer, and wherein the second protective layer has an etch resistancethat is greater than both the oxide layer and the first protectivelayer.
 26. The semiconductor structure of claim 7, wherein theprotective layer contains plasma species implanted therein in responseto undergoing a plasma treatment.
 27. The semiconductor structure ofclaim 24, wherein the fin protection liner includes a lower portioninterposed between the semiconductor substrate.
 28. The semiconductorstructure of claim 27 wherein the fin protection liner includes an upperportion on sidewalls and an upper surface of the plurality ofsemiconductor fins.
 29. The semiconductor structure of claim 28, whereinthe fin protection liner includes a lower portion interposed between thesemiconductor substrate.
 30. The semiconductor structure of claim 29,wherein the fin protection liner includes an upper portion on sidewallsand an upper surface of the plurality of semiconductor fins.